The present invention relates to nonvolatile memory devices and methods of fabricating the same and, more specifically, to phase changeable memory devices and fabrication methods therefor.
Semiconductor memory devices can be classified into volatile memory devices and nonvolatile memory devices. Volatile memory devices typically lose their stored data when their power supplies are interrupted. Nonvolatile (or “less volatile’) memory devices can typically retain their stored data for extended periods of time when their power supplies are interrupted. Accordingly, nonvolatile memory devices are widely used in such devices as memory cards and mobile communications devices.
Nonvolatile memory devices often employ flash memory cells having stacked gate structures. Each of the stacked gate structures typically includes a tunnel oxide layer, a floating gate, an inter-gate dielectric layer and a control gate electrode stacked on a channel region. In order to enhance reliability and program efficiency of such a flash memory cell, it is generally desirable to improve the film quality of the tunnel oxide layer and the coupling ratio of the cell.
A relatively new type of nonvolatile memory device, the phase changeable memory device, has been proposed for use in place of more conventional flash memory. As shown in FIG. 1, a conventional phase changeable memory cell includes a single access transistor TA and a single variable resistor C, which are serially connected to one another. The variable resistor C includes a bottom electrode, a top electrode and a phase changeable material layer interposed therebetween. The top electrode of the variable resistor C is connected to a plate electrode PL. The access transistor TA includes a source region connected to the bottom electrode, a drain region spaced apart from the source region and a gate electrode located on a channel region between the source and drain regions. The gate electrode and the drain region are electrically connected to a word line WL and a bit line BL, respectively.
An equivalent circuit of the phase changeable memory cell is similar to that of a typical dynamic random access memory (DRAM) cell. However, the phase changeable material layer is quite different from the dielectric layer typically employed in a DRAM cell capacitor. In particular, the phase changeable material layer exhibits two stable states according to temperature.
FIG. 2 is a graph for illustrating typical operations for writing data to a phase changeable memory cell. In the graph, the abscissa indicates time T and the ordinate indicates temperature TMP applied to the phase changeable material layer.
Referring to FIG. 2, in the event that the phase changeable material layer is heated to a temperature that is higher than a melting point temperature Tm thereof for a first duration T1 and then is cooled down rapidly, the phase changeable material layer is transformed into an amorphous state (curve 1). However, if the phase changeable material layer is instead heated to a temperature that is in a range between a crystallization temperature Tc thereof and the melting point temperature Tm for a second duration T2 longer than the first duration T1 and then is cooled down, the phase changeable material layer is transformed into a crystalline state (curve 2).
Generally, the resistivity of the phase changeable material layer in the amorphous state is higher than the resistivity of the phase changeable material layer in the crystalline state. Therefore, it is possible to discriminate whether the information stored in the memory cell is a logic “1” or a logic “0” by detecting the current that flows through the phase changeable material layer in a read operation. A compound material layer containing germanium (Ge), stibium (Sb) and tellurium (Te) (hereinafter referred to a GST layer) is widely used as a phase changeable material layer.
FIG. 3 is a cross-sectional view showing conventional phase changeable memory cells and operations for forming them. An isolation layer 13 defining an active region is disposed in a semiconductor substrate 11. A pair of parallel word lines 15 is disposed on and cross the active region. Impurity regions are formed at both sides of the pair of word lines 15, in particular, a common drain region 17d between the pair of word lines 15, and source regions 17s formed at respective ends of the active region. The substrate having the source/drain regions 17s and 17d, the word lines 15 and the isolation layer 13 is covered with a first interlayer insulation layer 19. A bit line 21 is disposed on the first interlayer insulation layer 19. The bit line 21 is electrically connected to the common drain region 17d. Only a portion of the bit line 21 is shown in the figure, but the bit line 21 crosses over the word lines 15.
The substrate including the bit line 21 is covered with a second interlayer insulation layer 23. Contact plugs 25 are disposed in the second interlayer insulation layer 23. Respective ones of the contact plugs 25 are electrically connected to the source regions 17s. A pair of phase changeable material layer patterns 27 is disposed on the second interlayer insulation layer 23. The phase changeable material layer patterns 27 cover respective ones of the contact plugs 25. Top electrodes 29 are disposed on the phase changeable material layer patterns 27. Gaps between the phase changeable material layer patterns 27 are filled with a planarized interlayer insulation layer 31. The planarized interlayer insulation layer 31 and the top electrodes 29 are covered with a plate electrode 33.
When a writing voltage is applied to the contact plug 25 of a selected cell A in order to write data to the selected cell A, heat is typically generated at the interface between the phase changeable material layer pattern 27 and the contact plug 25 of the selected cell A. Consequently, a portion 27a of the selected phase changeable material layer pattern 27 is transformed into an amorphous state. At this moment, heat generated in the selected cell A can be conducted to the phase changeable material layer pattern 27 of a non-selected cell B adjacent the selected cell A, through the conductive plate electrode 33 and/or the planarized interlayer insulation layer 31. Consequently, a portion 27b of the non-selected cell B may also be transformed into an amorphous state. As a result, the non-selected cell B can be weakly written due to this thermal transfer. The thermal interference phenomenon can increase as the space between the pair of cells A and B becomes narrower.
As mentioned above, the conventional phase changeable memory cells are formed at the same level. Thus, when a phase changeable memory cell is selectively written, a non-selected cell adjacent to the selected cell may be undesirably written.